Computers have become an integral tool used in a wide variety of different applications, such as in finance and commercial transactions, computer-aided design and manufacturing, health-care, telecommunication, education, etc. Computers are finding new applications as a result of advances in hardware technology and rapid development in software technology. Furthermore, a computer system's functionality is dramatically enhanced by coupling stand-alone computers together to form a computer network. In a computer network, users may readily exchange files, share information stored on a common database, pool resources, and communicate via e-mail and via video teleconferencing.
One popular type of computer network is known as a local area network (LAN). LANs connect multiple computers together such that the users of the computers can access the same information and share data. Typically, in order to be connected to a LAN, a general purpose computer requires an expansion board generally known as a network interface card (NIC). Essentially, the NIC works with the operating system and central processing unit (CPU) of the host computer to control the flow of information over the LAN. Some NICs may also be used to connect a computer to the Internet.
Much of a computer system's functionality and usefulness to a user is derived from the functionality of the peripheral devices. For example, the speed and responsiveness of the graphics adapter is a major factor in a computer system's usefulness as an entertainment device. Or, for example, the speed with which video files can be retrieved from a hard drive and played by the graphics adapter determines the computer system's usefulness as a training aid. Hence, the rate at which data can be transferred among the various peripheral devices often determines whether the computer system is suited for a particular purpose. The electronics industry has, over time, developed several types of bus architectures. Recently, the PCI (peripheral component interconnect) bus architecture has become one of the most widely used, widely supported bus architectures in the industry. The PCI bus was developed to provide a high speed, low latency bus architecture from which a large variety of systems could be developed.
Prior Art FIG. 1 shows a typical PCI bus architecture 100. PCI bus architecture 100 is comprised of a CPU 102, main memory 104, cache memory 105 all of which are coupled to a host PCI bridge containing arbiter 106 (hereafter arbiter 106) through a CPU local bus 108 and memory buses 110a and 110b, respectively. A PCI bus 112 is coupled to arbiter 106, and PCI bus 112 is further coupled to each of plurality of PCI agents 114, 116, 118, 120, 122, 124. Note that peripheral component 124 of Prior Art FIG. 1 is a NIC.
Referring still to Prior Art FIG. 1, each of PCI agents 114, 116, 118, 120, 122, 124 (hereafter, PCI agents 114-124) residing on PCI bus 112 use PCI bus 112 to transmit and receive data. PCI bus 112 is comprised of functional signal lines, for example, interface control lines, address/data lines, error signal lines, and the like. Each of PCI agents 114-124 are coupled to the functional signal lines comprising PCI bus 112. When one of PCI agents 114-124 requires the use of PCI bus 112 to transmit data, it requests PCI bus ownership from arbiter 106. The PCI agent requesting ownership is referred to as an "initiator", or bus master. Upon being granted ownership of PCI bus 112 from arbiter 106, the initiator (e.g., PCI agent 116) carries out its respective data transfer.
Each of PCI agents 114-124 may independently request PCI bus ownership. Thus, at any given time, several of PCI agents 114-124 may be requesting PCI bus ownership simultaneously. Where there are simultaneous requests for PCI bus ownership, arbiter 106 arbitrates between requesting PCI agents to determine which requesting PCI agent is granted PCI bus ownership. When one of PCI agents 114-124 is granted PCI bus ownership, it initiates it transaction (e.g., data transfer) with a "target " or slave device (e.g., main memory 104). When PCI agent relinquishes ownership of the PCI bus, arbiter 106 is able to reassign PCI bus 112 to another requesting PCI agent.
Thus, only one data transaction can take place on a PCI bus at any given time. In order to maximize the efficiency and data transfer bandwidth of PCI bus 112, PCI agents 114-124 follow a definitive set of protocols and rules. These protocols are designed to standardize the method of accessing, utilizing, and relinquishing PCI bus 112, so as to maximize its data transfer bandwidth. The PCI bus protocols and specifications are set forth in an industry standard PCI specification (e.g., PCI Specification--Revision 2.1). Where each of PCI agents 114-124 are high performance, well designed devices, data transfer rates of up to 528 Mbytes per second can be achieved (e.g., PCI bus 112 operating at 66 MHz and 64 bits wide).
The NIC, like other peripheral component devices, requires a device driver which controls the physical functions of the NIC and coordinates data transfers between the NIC and the host operating system. An industry standard for interfacing between the device driver and the host operating system is known as the Network Device Interface Specification, or NDIS, which is developed by Microsoft Corporation of Redmond, Washington. The operating system layer implementing the NDIS interface is generally known as an NDIS wrapper. Functionally, the NDIS wrapper arbitrates the control of the device driver between various application programs and provides temporary storage for the data packets.
During typical operation, NIC 124 will need to access (e.g. write data into) memory space of the host computer. In order perform such an operation, NIC 124 must obtain access to and utilize PCI bus 112. This process is sometimes referred to as "getting on the bus". Once on the bus, a conventional NIC will write the necessary data into cache memory space previously allocated to the NIC. Memory space is allocated to the NIC by the NIC driver operating in combination with operating system of the host computer.
In Prior Art systems, when writing to the cache, the NIC will typically perform either a Memory Write operation (MW), a Memory Write and Invalidate operation (MWI), or a combination of MW and MWI operations. When the transfer of data does not start on a cache line boundary or does not end on a cache line boundary a MW operation is used. On the other hand, a MWI operation, is used when the transfer of data from the peripheral component (e.g. NIC 124) starts on a cache line boundary and ends on a cache line boundary. Additionally, in order to use the MWI operation, all of the byte enables must always be asserted, thereby indicating that all bytes are in the cache line are being written.
Several benefits are associated with the MWI operation. For example, in many PCI-based systems, the MWI operation provides for bursting of significant amounts of data (enough data to occupy at least one cache line) from the NIC to the cache. Furthermore, because the NIC is writing to an entire cache line, the MWI operation invalidates all data in the allocated cache line(s). Hence, the memory subsystem of the host computer is informed that the data in that cache line is invalid. Therefore, the memory subsystem of the host computer does not need to check and/or update that particular line of the cache and write it back to main memory. As a result, CPU utilization is reduced. Additionally, the MWI operation is able to write to multiple lines of the cache memory without relinquishing control of the bus. Unfortunately, as stated above, the MWI operation can only be used when the transfer of data from the NIC starts on a cache line boundary and ends on a cache line boundary.
Therefore, commonly, data transfers from a peripheral component to the cache of the host computer are performed using both a MW and a MWI operation. For example, data starting on a cache line boundary and ending on a cache line boundary is transferred using the MWI operation. Remaining data to be transferred, which does not start or end on a cache line boundary, is then transferred using the MW operation. However, in order to transition from one operation to another (e.g. MWI to MW, or from MW to MWI), the peripheral component must relinquish ownership of the bus (this process is sometimes referred to as "getting off the bus"), and then regain access to and control of the bus. Although the peripheral component is writing data to memory space of the host computer, for cache coherency purposes, the system must update any modified bits in the cache memory to main memory. By using the MWI operation, this updating process does need to be performed.
In one example of a conventional operation, a first portion of data to be placed in the memory of the host computer system is transferred from the peripheral component to the cache using a MWI operation. After the first portion of the data has been transferred, the peripheral component gets off the bus. Once off the bus, the peripheral component must then get back on the bus again in order to transfer the remaining/second portion of the data using the MW operation. However, even if no other components are requesting access to the bus, several clock cycles of latency are associated with requesting and being granted ownership of the bus. If other peripheral components are requesting or have been granted ownership of the bus, it may be an extended period of time before the original peripheral component is able to perform the MW operation and complete the transfer of the second portion of the data to the cache.
Thus, a need exists for a system and method which provides for a more efficient transfer of data between a peripheral component and the cache memory of a host computer system. A need also exists for a system and method which minimizes the CPU overhead associated with data transfers between a peripheral component and the cache memory of a host computer system. Still another need exists for a system and method which reduces the latency associated with data transfers between a peripheral component and the cache memory of a host computer system.